This invention relates generally to electronic devices, and more particularly to a method for two-sided fabrication of a memory array.
Modern electronic equipment such as televisions, telephones, radios and computers are generally constructed of solid state devices. Solid state devices are preferred in electronic equipment because they are extremely small and relatively inexpensive. Additionally, solid state devices are very reliable because they have no moving parts, but are based on the movement of charge carriers.
Solid state devices may be transistors, capacitors, resistors, and other semiconductor devices. Typically, such devices are fabricated on a substrate and interconnected to form memory arrays, logic structures, timers, and other integrated circuits. One type of memory array is a dynamic random access memory (DRAM) in which memory cells retain information only temporarily and are refreshed at periodic intervals. Despite this limitation, DRAMs are widely used because they provide low cost per bit of memory, high device density, and feasibility of use.
In a DRAM, each memory cell typically includes an access transistor coupled to a storage capacitor. In order to fabricate high density DRAMs, the storage capacitors must take up less planar area in the memory cells. As storage capacitors are scaled down in dimensions, a sufficiently high storage capacity must be maintained. Efforts to maintain storage capacity have concentrated on building three-dimensional capacitor structures that increase the capacitor surface area. The increased surface area provides for increased storage capacity. Three-dimensional capacitor structures include trench capacitors and stacked capacitors.
For stacked capacitors, the storage node generally extends significantly above the surface of an underlying substrate in order to provide a large surface area and thus sufficient storage capacity. This leads to topological problems in the formation of subsequent layers in the DRAM. Such topological problems are reduced by the use of crown-type stacked capacitors that increase surface area of the storage node while minimizing height. Crown-type capacitors, however, have a high process complexity which leads to high fabrication cost and low yield.
In accordance with the present invention, a method for two-sided fabrication of a memory array or other integrated circuit is provided that substantially eliminates or reduces disadvantages and problems associated with previously developed systems and methods. In particular, the present invention provides a method for fabricating a portion of the integrated circuit on a backside of the underlying substrate that improves circuit topology and thereby reduces device overlap, processing complexity, and fabrication costs.
In one embodiment of the present invention, a method for fabricating a memory array includes fabricating a first portion of a memory array on a first side of a substrate. A second portion of the memory array is fabricated on a second, opposite side of the substrate. The first and second portions of the memory array are coupled to each other through the substrate.
More specifically, in accordance with one embodiment of the present invention, the first portion of the memory array includes first and second terminals defining an access channel for each memory cell of the array and a storage node connected to the first terminal for the memory cell. In this embodiment, the access channel may be formed in a discrete post or in an elongated projection. The first and second terminals may be formed in or adjacent to the discrete post or the elongated projection. The second portion of the memory array includes a gate structure for each memory cell. The gate structure is operable to control the access channel to allow access to the storage node from the second terminal.
Technical advantages of the present invention include providing an improved method for fabricating a memory array. In particular, a portion of the memory array is fabricated on a backside of the underlying substrate. As a result, topology of the memory array is improved, which reduces process complexity and cost while increasing yield.
Another technical advantage of the present invention includes providing an improved method for fabricating a memory cell. In particular, a storage node for the memory cell is fabricated on an opposite side of a substrate from word lines, bit lines, or other components of the memory cell. This allows the use of storage node materials that would otherwise conflict with the other components of the memory array and also allows the height of the storage nodes to be increased without causing topological problems in the memory array. Accordingly, the storage node capacitance is increased without increasing fabrication costs. In addition, taller and less complex storage node configurations may be used that reduce cost and increase yield.
Still another technical advantage of the present invention includes providing a very high density gate device for memory arrays and other integrated circuits. In particular, the gate device has a raised channel with individual source and drain terminals. The channels may be continuous or may be separated into discrete posts. In either case, the use of individual source and drain terminals allows the gate device to be scaled down to minimal isolation between devices.
Other technical advantages of the present invention will be readily apparent to one skilled in the art from the following figures, description, and claims.